Low-cost parallel FIR filter structures with 2-stage parallelism

被引:23
作者
Cheng, Chao [1 ]
Parhi, Keshab K. [1 ]
机构
[1] Univ Minnesota, Dept Elect & Comp Engn, Minneapolis, MN 55455 USA
基金
美国国家科学基金会;
关键词
fast convolution; iterated short convolution (ISC); parallel finite-impulse response (FIR); VLSI;
D O I
10.1109/TCSI.2006.885976
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Based on recently published low-complexity parallel finite-impulse response (FIR) filter structures, this paper proposes a new parallel FIR Filter structure with less hardware complexity. The subfilters in the previous parallel FIR structures are replaced by a second stage parallel FIR filter. The proposed 2-stage parallel FIR filter structures can efficiently reduce the number of required multiplications and additions at the expense of delay elements. For a 32-parallel 1152-tap FIR filter, the proposed structure can save 5184 multiplications (67%), 2612 additions (30%), compared to previous parallel FIR structures, at the expense of 10089 delay elements (-133%). The proposed structures will lead to significant hardware savings because the hardware cost of a delay element is only a small portion of that of a multiplier, not including the savings in the number of additions.
引用
收藏
页码:280 / 290
页数:11
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