Design of transport triggered architecture processor for discrete cosine transform

被引：2
|
作者：
Heikkinen, J [1 ]
Sertamo, J [1 ]
Rautiainen, T [1 ]
Takala, J [1 ]
机构：
[1] Tampere Univ Technol, FIN-33101 Tampere, Finland
来源：
15TH ANNUAL IEEE INTERNATIONAL ASIC/SOC CONFERENCE, PROCEEDINGS | 2002年
关键词：
D O I：
10.1109/ASIC.2002.1158036
中图分类号：
TP31 [计算机软件];
学科分类号：
081202 ; 0835 ;
摘要：
The trend in programmable architectures for digital signal processing is to move towards high-level language programming and customizable architectures. Several design methodologies have been proposed for designing application-specific instruction-set processors (ASIP) where the hardware resources are tailored according to the requirements of the application. This paper describes the design of an ASIP for a 32-point discrete cosine transform using the tools from the MOVE framework, which is a semi-automatic design methodology for designing processors that utilize the paradigm of transport triggered architecture. Estimations of the designed processor are obtained on program execution, code size, timing and area.
引用
收藏
页码：87 / 91
页数：5
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