Easily testable implementation for bit parallel multipliers in GF (2m)

被引:0
作者
Rahaman, H. [1 ]
Mathew, J. [1 ]
Jabir, A. M. [2 ]
Pradhan, D. K. [1 ]
机构
[1] Univ Bristol, Dept Comp Sci, Bristol BS8 1UB, Avon, England
[2] Oxford Brookes Univ, Sch Technol, Oxford OX3 0BP, England
来源
HLDVT'06: ELEVENTH ANNUAL IEEE INTERNATIONAL HIGH-LEVEL DESIGN VALIDATION AND TEST WORKSHOP, PROCEEDINGS | 2006年
基金
英国工程与自然科学研究理事会;
关键词
stuck-at fault; Built-in Self-Test (BIST); Finite or Galois field; Mastrovito multiplier; cryptography; error control code;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
A testable implementation of bit parallel multiplier over the finite field GF(2(m)) is proposed A function independent test set of length (2m+4), which detects all the single stuck-at faults in an m bit GF(2(m)) multiplier circuit, is also presented Test set can be determined readily from the corresponding algebraic forms without running an ATPG tool. The test complexity is lower than ATPG generated or algorithmic test set. The test set provides 100 percent single stuck-at fault coverage The gate counts of the proposed testable multiplier as a function of degree in has been analyzed The testable circuit realization requires only two extra inputs for controllability and some additional FXOR gates to enhance the testability. As the GF(2(m)) multipliers have found some critical field applications and need field testing, Built-in Self-Test (BIST) circuit may be used to generate test pattern internally for detecting faults in the multiplier circuits.
引用
收藏
页码:48 / +
页数:2
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