共 50 条
- [21] Analysis of timing jitter in inverters induced by power-supply noise [J]. IEEE DTIS: 2006 INTERNATIONAL CONFERENCE ON DESIGN & TEST OF INTEGRATED SYSTEMS IN NANOSCALE TECHNOLOGY, PROCEEDINGS, 2006, : 53 - 56
- [22] Test-Point Insertion for Power-Safe Testing of Monolithic 3D ICs using Reinforcement Learning [J]. 2023 IEEE EUROPEAN TEST SYMPOSIUM, ETS, 2023,
- [25] Co-design of Reliable Signal and Power Interconnects in 3D Stacked ICs [J]. PROCEEDINGS OF THE 2009 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2009, : 56 - 58
- [27] Testing and Fault-Localization Solutions for Monolithic 3D ICs [J]. 2021 IEEE INTERNATIONAL TEST CONFERENCE IN ASIA (ITC-ASIA 2021), 2021,
- [28] Design and CAD Methodologies for Low Power Gate-level Monolithic 3D ICs [J]. PROCEEDINGS OF THE 2014 IEEE/ACM INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN (ISLPED), 2014, : 171 - 176
- [29] Hetero-3D: Maximizing Performance and Power Delivery Benefits of Heterogeneous 3D ICs [J]. PROCEEDINGS OF THE 29TH ACM/IEEE INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, ISLPED 2024, 2024,
- [30] New Power Delivery Scheme for 3D ICs to Minimize Simultaneous Switching Noise for High Speed I/Os [J]. 2012 IEEE 21ST CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS, 2012, : 87 - 90