Reliable Power Delivery and Analysis of Power-Supply Noise During Testing in Monolithic 3D ICs

被引:0
作者
Koneru, Abhishek [1 ]
Todri-Sanial, Aida [2 ]
Chakrabarty, Krishnendu [1 ]
机构
[1] Duke Univ, Dept Elect & Comp Engn, Durham, NC 27708 USA
[2] Univ Montpellier II, CNRS, LIRMM, Montpellier, France
来源
2019 IEEE 37TH VLSI TEST SYMPOSIUM (VTS) | 2019年
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Monolithic 3D (M3D) integration offers significant performance, power, and area benefits. However, the design of a reliable M3D power-delivery network (PDN) is challenging due to high power density and current demand per unit area. We propose a framework to design a reliable PDN for M3D ICs using accurate electrical and reliability models. We leverage genetic programming to explore the design space to optimize the PDN for M3D. We also analyze power-supply noise (PSN) during scan-based testing and compare it with that observed during functional operation. We quantify the impact of PSN during scan-based testing on yield loss. Our results show that the PDN obtained using the proposed approach significantly increases the reliability of at least 40% of the wire segments in the PDN. In addition, the proposed PDN design reduces the worst-case power-supply droop by 50.5% compared to a baseline PDN. The yield loss due to power-supply droop for the proposed design is also significantly lower compared to the baseline.
引用
收藏
页数:6
相关论文
共 50 条
  • [21] Analysis of timing jitter in inverters induced by power-supply noise
    Strak, Adain
    Tenhunen, Hannu
    [J]. IEEE DTIS: 2006 INTERNATIONAL CONFERENCE ON DESIGN & TEST OF INTEGRATED SYSTEMS IN NANOSCALE TECHNOLOGY, PROCEEDINGS, 2006, : 53 - 56
  • [22] Test-Point Insertion for Power-Safe Testing of Monolithic 3D ICs using Reinforcement Learning
    Hung, Shao-Chun
    Chaudhuri, Arjun
    Chakrabarty, Krishnendu
    [J]. 2023 IEEE EUROPEAN TEST SYMPOSIUM, ETS, 2023,
  • [23] Pattern generation for delay testing and dynamic timing analysis considering power-supply noise effects
    Krstic, A
    Jiang, YM
    Cheng, KT
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2001, 20 (03) : 416 - 425
  • [24] An Algorithm for Power Supply Noise Reduction Inserting Decoupling Capacitor in 2D and 3D IC Power Delivery Networks
    Mondal, Khokan
    Samanta, Tuhina
    [J]. IETE JOURNAL OF RESEARCH, 2024, 70 (01) : 638 - 648
  • [25] Co-design of Reliable Signal and Power Interconnects in 3D Stacked ICs
    Lee, Young-Joon
    Healy, Mike
    Lim, Sung Kyu
    [J]. PROCEEDINGS OF THE 2009 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2009, : 56 - 58
  • [26] Voltage Optimization of Power Delivery Networks through Power Bump and TSV Placement in 3D ICs
    Jang, Cheoljon
    Chong, Jong-wha
    [J]. ETRI JOURNAL, 2014, 36 (04) : 642 - 652
  • [27] Testing and Fault-Localization Solutions for Monolithic 3D ICs
    Chaudhuri, Arjun
    Chakrabarty, Krishnendu
    [J]. 2021 IEEE INTERNATIONAL TEST CONFERENCE IN ASIA (ITC-ASIA 2021), 2021,
  • [28] Design and CAD Methodologies for Low Power Gate-level Monolithic 3D ICs
    Panth, Shreepad
    Samadi, Kambiz
    Du, Yang
    Lim, Sung Kyu
    [J]. PROCEEDINGS OF THE 2014 IEEE/ACM INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN (ISLPED), 2014, : 171 - 176
  • [29] Hetero-3D: Maximizing Performance and Power Delivery Benefits of Heterogeneous 3D ICs
    Zhu, Lingjun
    Hu, Jiawei
    Murali, Gauthaman
    Lim, Sung Kyu
    [J]. PROCEEDINGS OF THE 29TH ACM/IEEE INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, ISLPED 2024, 2024,
  • [30] New Power Delivery Scheme for 3D ICs to Minimize Simultaneous Switching Noise for High Speed I/Os
    Zhang, David C.
    Swaminathan, Madhavan
    Huh, Suzanne
    [J]. 2012 IEEE 21ST CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS, 2012, : 87 - 90