Analytical Modeling of Flicker Noise in Halo Implanted MOSFETs

被引：17

作者：

Agarwal, Harshit ^{[1
]}

Khandelwal, Sourabh ^{[2
]}

Dey, Sagnik ^{[3
]}

Hu, Chenming ^{[2
]}

Chauhan, Yogesh Singh ^{[1
]}

机构：

[1] Indian Inst Technol, Dept Elect Engn, Nanolab, Kanpur 208016, Uttar Pradesh, India

[2] Univ Calif Berkeley, Dept Elect Engn & Comp Sci, Berkeley, CA 94720 USA

[3] Texas Instruments Inc, Embedded Proc Technol Dev, SPICE Modeling Lab, Dallas, TX 75243 USA

来源：

IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY | 2015年 / 3卷 / 04期

关键词：

BSIM6; halo doping; flicker noise; compact model; 1/F NOISE; DEGRADATION; ANALOG;

D O I：

10.1109/JEDS.2015.2424686

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An improved analytical model for flicker noise (1/f noise) in MOSFETs is presented. Current models do not capture the effect of high-trap density in the halo regions of the devices, which leads to significantly different bias dependence of flicker noise across device geometry. The proposed model is the first compact model implementation capturing such effect and show distinct improvements over other existing noise models. The model is compatible with BSIM6, the latest industry standard model for bulk MOSFET, and is validated with measurements from 45-nm low-power CMOS technology node.

引用

页码：355 / 360

页数：6

共 25 条

[1]

Agarwal H, 2013, 2013 18TH INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES (SISPAD 2013), P53, DOI 10.1109/SISPAD.2013.6650572

[2]

Agarwal H., 2014, P WORKSH COMP MOD WA

[3] Analytical Modeling and Experimental Validation of Threshold Voltage in BSIM6 MOSFET Model [J].

Agarwal, Harshit ;

Gupta, Chetan ;

Kushwaha, Pragya ;

Yadav, Chandan ;

Duarte, Juan P. ;

Khandelwal, Sourabh ;

Hu, Chenming ;

Chauhan, Yogesh S. .

IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2015, 3 (03) :246-249

[4] Degradation of 1/f noise in short channel MOSFETs due to halo angle induced VT non-uniformity and extra trap states at interface [J].

Ahsan, A. K. M. ;

Ahmed, Shaikh .

SOLID-STATE ELECTRONICS, 2006, 50 (11-12) :1705-1709

[5]

[Anonymous], 2014, BSIM6 1 0 MOSFET COM

[6]

[Anonymous], 2013, BSIM4 TECHNICAL MANU

[7] New Cost-Effective Integration Schemes Enabling Analog and High-Voltage Design in Advanced CMOS SOC Technologies [J].

Benaissa, K. ;

Baldwin, G. ;

Liu, S. ;

Srinivasan, P. ;

Hou, F. ;

Obradovic, B. ;

Yu, S. ;

Yang, H. ;

McMullan, R. ;

Reddy, V. ;

Chancellor, C. ;

Venkataraman, S. ;

Lu, H. ;

Dey, S. ;

Cirba, C. .

2010 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2010, :221-222

[8] HIGH-FREQUENCY FET NOISE PERFORMANCE - A NEW APPROACH [J].

CAPPY, A ;

HEINRICH, W .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1989, 36 (02) :403-409

[9] BSIM6: Analog and RF Compact Model for Bulk MOSFET [J].

Chauhan, Yogesh Singh ;

Venugopalan, Sriramkumar ;

Chalkiadaki, Maria-Anna ;

Ul Karim, Muhammed Ahosan ;

Agarwal, Harshit ;

Khandelwal, Sourabh ;

Paydavosi, Navid ;

Duarte, Juan Pablo ;

Enz, Christian C. ;

Niknejad, Ali M. ;

Hu, Chenming .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2014, 61 (02) :234-244

[10]

Enz C.C., 2006, Charge-based MOS transistor modeling: the EKV model for low-power and RF IC design

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