Implementing a self-timed low-power java']java accelerator for network-on-chip applications

被引：0

作者：

Liang, Zheng ^{[1
]}

Plosila, Juha ^{[1
]}

Yan, Lu ^{[1
]}

Sere, Kaisa ^{[1
]}

机构：

[1] Turku Ctr Comp Sci, Turku, Finland

来源：

SEVENTH INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED COMPUTING, APPLICATIONS AND TECHNOLOGIES, PROCEEDINGS | 2006年

关键词：

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

This paper presents an advanced self-timed Java accelerator core which has extremely low power consumption while providing sufficient performance for even the most demanding real-time telecommunication and multimedia applications. The goal is that the accelerator can be directly attached to any general-purpose processor core running some Java-intensive application software. Asynchronous self-timed circuit technology, where timing is based on local handshakes between circuit blocks instead of a global clock signal, provides a promising platform for obtaining a highly modular low-power Java accelerator implementation.

引用

页码：344 / +

页数：2

共 50 条

[41] Implementing Cellular Automata modeled applications on Network-on-Chip platforms
Zompakis, N.
Papadopoulos, L.
Sirakoulis, G.
Soudris, D.
VLSI-SOC 2007: PROCEEDINGS OF THE 2007 IFIP WG 10.5 INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION, 2007, : 288 - 291
[42] A Low-Power Fat Tree-based Optical Network-on-Chip for Multiprocessor System-on-Chip
Gu, Huaxi
Xu, Jiang
Zhang, Wei
DATE: 2009 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, VOLS 1-3, 2009, : 3 - +
[43] Adaptive Body Bias Control Scheme for Ultra Low-power Network-on-Chip Systems
Ben Ahmed, Akram
Okuhara, Hayate
Matsutani, Hiroki
Koibuchi, Michihiro
Amano, Hideharu
2018 IEEE 12TH INTERNATIONAL SYMPOSIUM ON EMBEDDED MULTICORE/MANY-CORE SYSTEMS-ON-CHIP (MCSOC 2018), 2018, : 146 - 153
[44] Low-cost and low-power unidirectional torus network-on-chip with corner buffer power-gating
Wang, Feng
Tang, Xiantuo
Xing, Zuocheng
Liu, Hengzhu
INTERNATIONAL JOURNAL OF ELECTRONICS, 2016, 103 (08) : 1332 - 1348
[45] Low power Java processor for embedded applications
Beck, Antonio Carlos S.
Carro, Luigi
IFIP Advances in Information and Communication Technology, (213-228):
[46] Flexible Virtual Channel Power-Gating for High-Throughput and Low-Power Network-on-Chip
Wang, Feng
Tang, Xiantuo
Wang, Qinglin
Xing, Zuocheng
Liu, Hengzhu
2014 17TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD), 2014, : 504 - 511
[47] F-Bypass: A Low-Power Network-on-Chip Design Utilizing Bypass to Improve Network Connectivity
Ouyang, Yiming
Yuan, Shuaijie
Li, Jianhua
Liang, Huaguo
ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, 2024, 20 (04)
[48] Low-power low-area network-on-chip architecture using adaptive electronic link buffers
Sarathy, A.
Kodi, A. K.
Louri, A.
ELECTRONICS LETTERS, 2008, 44 (08) : 512 - 513
[49] Low-power optical network-on-chip using low-loss multilayer silicon wire waveguide
Jyoti Kedia
Anurag Sharma
Neena Gupta
Journal of Optics, 2019, 48 : 557 - 566
[50] Low-power optical network-on-chip using low-loss multilayer silicon wire waveguide
Kedia, Jyoti
Sharma, Anurag
Gupta, Neena
JOURNAL OF OPTICS-INDIA, 2019, 48 (04): : 557 - 566

← 1 2 3 4 5 →