Implementing a self-timed low-power java']java accelerator for network-on-chip applications

被引：0

作者：

Liang, Zheng ^{[1
]}

Plosila, Juha ^{[1
]}

Yan, Lu ^{[1
]}

Sere, Kaisa ^{[1
]}

机构：

[1] Turku Ctr Comp Sci, Turku, Finland

来源：

SEVENTH INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED COMPUTING, APPLICATIONS AND TECHNOLOGIES, PROCEEDINGS | 2006年

关键词：

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

This paper presents an advanced self-timed Java accelerator core which has extremely low power consumption while providing sufficient performance for even the most demanding real-time telecommunication and multimedia applications. The goal is that the accelerator can be directly attached to any general-purpose processor core running some Java-intensive application software. Asynchronous self-timed circuit technology, where timing is based on local handshakes between circuit blocks instead of a global clock signal, provides a promising platform for obtaining a highly modular low-power Java accelerator implementation.

引用

页码：344 / +

页数：2

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