A new vertical channel LDMOS

被引：1

作者：

Lee, SC ^{[1
]}

Oh, JK

Han, MK

Choi, YI

机构：

[1] Seoul Natl Univ, Sch Elect Engn, Seoul 151742, South Korea

[2] Ajou Univ, Sch Elect Engn, Suwon 441749, South Korea

来源：

PHYSICA SCRIPTA | 2002年 / T101卷

关键词：

D O I：

10.1238/Physica.Topical.101a00058

中图分类号：

O4 [物理学];

学科分类号：

0702 ;

摘要：

A new vertical channel LDMOS, which decreases the on-resistance without sacrificing the breakdown voltage, is proposed and verified by numerical simulation. In the proposed vertical channel LDMOS, the channel and the drift region are located in the trench between the source and the drain. The total cell pitch of the proposed device is decreased to 4 mum which is about a half of the conventional LDMOS when the breakdown voltage is 60 V Simulation results show that the on-resistance is 0.45 mOmega.cm(2) for a 60 V breakdown voltage which is very low compared to that of the conventional LDMOS.

引用

页码：58 / 60

页数：3

共 7 条

[1]

Efland T., 1992, International Electron Devices Meeting 1992. Technical Digest (Cat. No.92CH3211-0), P237, DOI 10.1109/IEDM.1992.307350

[2]

EFLAND T, 1996, SELF ALIGNED RESURF

[3]

FUJISHIMA M, 1997, IEDM, P359

[4]

TAI CY, 1997, 16 60V RAT LDMOS SHO

[5]

*TECHN MOD ASS INC, 1998, TSUPR US MAN VERS 98

[6]

*TECHN MOD ASS INC, 2000, MEDICI US MAN VERS 1

[7] A 65V, 0.56 mΩ.cm2 resurf LDMOS in a 0.35 μm CMOS process [J].

Zhu, R ;

Parthasarathy, V ;

Bose, A ;

Baird, R ;

Khemka, V ;

Roggenbauer, T ;

Collins, D ;

Chang, S ;

Hui, P ;

Ger, ML ;

Zunino, M .

12TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES & ICS - PROCEEDINGS, 2000, :335-338

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