Air Spacer for 10nm FinFET CMOS and Beyond

被引：0

作者：

Cheng, K. ^{[1
]}

Park, C. ^{[2
]}

Yeung, C. ^{[1
]}

Nguyen, S. ^{[1
]}

Zhang, J. ^{[1
]}

Miao, X. ^{[1
]}

Wang, M. ^{[1
]}

Mehta, S. ^{[1
]}

Li, J. ^{[1
]}

Surisetty, C. ^{[1
]}

Muthinti, R. ^{[1
]}

Liu, Z. ^{[1
]}

Tang, H. ^{[1
]}

Tsai, S. ^{[1
]}

Yamashita, T. ^{[1
]}

Bu, H. ^{[1
]}

Divakaruni, R. ^{[1
]}

机构：

[1] IBM Corp, 257 Fuller Rd, Albany, NY 12203 USA

[2] GLOBALFOUNDRIES, 257 Fuller Rd, Albany, NY 12203 USA

来源：

2016 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2016年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

For the first time, we report integration of air spacers with FinFET technology at 10nm node dimensions. The benefit of parasitic capacitance reduction by air spacers has been successfully demonstrated both at transistor level (15-25% reduction in overlap capacitance (G(ov))) and at ring oscillator level (10-15% reduction in effective capacitance (C-eff)). Key process challenges and device implications of integrating air spacers in FinFET are identified. We propose a partial air spacer scheme, in which air spacers are formed only above fin top and sandwiched by two dielectric liners, as a viable option to adopt air spacers in FinFET technology with minimal risks to yield and reliability.

引用

页数：4

共 14 条

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