A platform-based design framework for joint SW/HW multiprocessor systems design

被引：4

作者：

Assayad, Ismail ^{[1
]}

机构：

[1] Verimag Ctr Equat, F-38610 Gieres, France

来源：

JOURNAL OF SYSTEMS ARCHITECTURE | 2009年 / 55卷 / 7-9期

关键词：

Joint software and hardware modelling; Joint software and hardware synthesis; Software and hardware performance; Transactional-level modelling; SOC DESIGN; FLOW; CHIP;

D O I：

10.1016/j.sysarc.2009.08.001

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We present P-WARE, a framework for joint software and hardware modelling and synthesis of multiprocessor embedded systems. The framework consists of (I) component-based annotated transaction-level models for joint modelling of parallel software and multiprocessor hardware, and (2) exploration-driven methodology for joint software and hardware synthesis. The methodology has the advantage of combining real-time requirements of software with efficient optimization of hardware performance. We describe and apply the methodology to synthesize a scheduler of a H264 video encoder on the Cake multiprocessor. Moreover, experiments show that the framework is scalable while achieving rapid and efficient designs. (C) 2009 Elsevier B.V. All rights reserved.

引用

页码：409 / 420

页数：12