Mixed-Mode Simulation of Common Emitter Amplifier Design using Bipolar Charge Plasma Transistor

被引：0
|
作者：
Agrawal, Nitesh [1 ]
Sahu, Chitrakant [2 ]
机构：
[1] RCOEM, Nagpur, Maharashtra, India
[2] Malviy Natl Inst Technol Jaipur, Jaipur, Rajasthan, India
来源：
PROCEEDINGS OF 2016 IEEE INTERNATIONAL SYMPOSIUM ON NANOELECTRONIC AND INFORMATION SYSTEMS (INIS) | 2016年
关键词：
BiCMOS; BCPT; frequency response;
D O I：
10.1109/iNIS.2016.37
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, we have shown frequency response analysis of common-emitter (CE) amplifier using bipolar charge plasma transistor (BCPT) with a device-circuit approach of mixed-mode simulation. Furthermore, the passive elements are adjusted to obtain the proper operating point (Q-point) of the circuit. The mixed-mode simulation results exhibits that maximum gain of the BJT, symmetric BCPT and asymmetric BCPT are 7.3 dB, 13.5 dB, and 13.7 dB, respectively and unity gain frequency are 813 GHz, 116 GHz, and 132 GHz, respectively. The mixed-mode simulation frequency response is also validated using transfer function equation containing pole and zero through MATLAB.
引用
收藏
页码：149 / 154
页数：6
相关论文
共 50 条
  • [1] Original amplifier using only emitter and base of a Si bipolar transistor
    Okamoto, Kensho
    Fujita, Junichi
    Ishikawa, Masaki
    Hattori, Tetsuo
    2014 IEEE INTERNATIONAL MEETING FOR FUTURE OF ELECTRON DEVICES, KANSAI (IMFEDK), 2014,
  • [2] WIDEBAND MATCHED AMPLIFIER DESIGN USING DUAL LOOP FEEDBACK AND 2 COMMON EMITTER TRANSISTOR STAGES
    APRILLE, TJ
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1976, 23 (07): : 434 - 442
  • [3] MIXED-MODE CIRCUIT SIMULATION USING DYNAMIC PARTITIONING
    NISHIGAKI, M
    TANAKA, N
    ASAI, H
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 1993, E76A (03) : 292 - 298
  • [4] Emitter scaling dependence of mixed-mode reliability degradation in silicon-germanium heterojunction bipolar transistors
    Lee, Seung-Yun
    Zhu, Chendong
    Cressler, John D.
    Lee, Sang-Heung
    JAPANESE JOURNAL OF APPLIED PHYSICS, 2008, 47 (07) : 5309 - 5313
  • [5] Mixed-mode ESD protection circuit simulation-design methodology
    Feng, H
    Wu, Q
    Chen, G
    Guan, X
    Xie, H
    Wang, AZ
    Zhan, R
    PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL IV: DIGITAL SIGNAL PROCESSING-COMPUTER AIDED NETWORK DESIGN-ADVANCED TECHNOLOGY, 2003, : 652 - 655
  • [6] Voltage Regulators Design Through Advanced Mixed-Mode Circuit Simulation
    Bizzarri, F.
    Brambilla, A.
    Saggini, S.
    IEEE TRANSACTIONS ON POWER ELECTRONICS, 2014, 29 (09) : 4496 - 4499
  • [7] A mixed-mode ESD protection circuit simulation-design methodology
    Feng, HG
    Chen, G
    Zhan, RY
    Wu, Q
    Guan, XK
    Xie, HL
    Wang, AZH
    Gafiteanu, R
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2003, 38 (06) : 995 - 1006
  • [8] Design and performance projection of symmetric bipolar charge-plasma transistor on SOI
    Sahu, C.
    Ganguly, A.
    Singh, J.
    ELECTRONICS LETTERS, 2014, 50 (20) : 1461 - 1462
  • [9] Optimizing the simulation of bipolar transistor packages using sliding mode techniques
    Mkrttchian, V
    Simonyan, A
    Mkrtchyan, K
    DESIGN, CHARACTERIZATION, AND PACKAGING FOR MEMS AND MICROELECTRONICS, 1999, 3893 : 388 - 395
  • [10] USING VHDL FOR HIGH-LEVEL, MIXED-MODE SYSTEM SIMULATION
    SRIVASTAVA, MB
    BRODERSEN, RW
    IEEE DESIGN & TEST OF COMPUTERS, 1992, 9 (03): : 31 - 40
12345