8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology

被引：228

作者：

Kang, Uksong ^{[1
]}

Chung, Hoe-Ju ^{[1
,2
]}

Heo, Seongmoo

Park, Duk-Ha

Lee, Hoon

Kim, Jin Ho

Ahn, Soon-Hong

Cha, Soo-Ho

Ahn, Jaesung ^{[3
]}

Kwon, DukMin

Lee, Jae-Wook

Joo, Han-Sung

Kim, Woo-Seop

Jang, Dong Hyeon

Kim, Nam Seog

Choi, Jung-Hwan

Chung, Tae-Gyeong

Yoo, Jei-Hwan

Choi, Joo Sun

Kim, Changhyun

Jun, Young-Hyun

机构：

[1] Samsung Elect, DRAM Dev Team, Hwasung 445701, Gyeonggi Do, South Korea

[2] Samsung Elect, PRAM Phase Change RAM Dev Team, Hwasung 445701, Gyeonggi Do, South Korea

[3] Samsung Elect Co, Device Solut Business, Hwasung 445701, Gyeonggi Do, South Korea

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2010年 / 45卷 / 01期

关键词：

Through-silicon-via (TSV); via last; via middle; via first; three dimensional; 3-D architecture; stack; master; slave; DDR3; DRAM; double data rate; rank; module; connectivity check and repair; assembly yield; power noise reduction; refresh; power edge pads; seamless; gapless read; INTEGRATION;

D O I：

10.1109/JSSC.2009.2034408

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An 8 Gb 4-stack 3-D DDR3 DRAM with through-Si-via is presented which overcomes the limits of conventional modules. A master-slave architecture is proposed which decreases the standby and active power by 50 and 25%, respectively. It also increases the I/O speed to > 1600 Mb/s for 4 rank/module and 2 module/channel case since the master isolates all chip I/O loadings from the channel. Statistical analysis shows that the proposed TSV check and repair scheme can increase the assembly yield up to 98%. By providing extra VDD/VSS edge pads, power noise is reduced to < 100 mV even if all 4 ranks are refreshed every clock cycle consecutively.

引用

页码：111 / 119

页数：9

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