A Series-parallel Mixed Structure FFT Processor

The proposed fixed-point radix-2 decimation-in-time Fast Fourier Transform (R2DIT FFT) processor is implemented by the series-parallel mixed structure. The 64-point FFT is decomposed into 8-channel 8-point FFT structure. Each channel is a serial 8-point FFT which uses an 8-point full-parallel structure. The vertical 8-channel 8-point FFT is calculated, then the result is multiplied by W-N(n1k2). After that, the horizontal 8-channel 8-point FFT is calculated. In this way, the 64-point FFT calculation is decomposed into two full-parallel 8-point FFT calculations. The processing of the 64-point FFT calculation takes about 1.96 mu s at 100 MHz based on EP2S130F1020C3 chip. And the output from the first data to the last data spends about 0.76 mu s. Then, the 64-point FFT is simplified to the 16-point FFT with the same series-parallel mixed structure and downloaded to the EP2C35F-672C6 chip of the DE2 FPGA development board. Then the signal is extracted with the SignalTap II tool. Experimental values are compared with theoretical values calculated by Matlab. After converting them to decimal fractions, the absolute error is less than 0.2. In addition, it takes about 9.8 mu s from the data input to the first data output at 100 MHz. And the total output from the first data output to the last data output is about 3 Vas. Compared with the full-parallel FFT, the series-parallel mixed structure scheme achieves an effective solution for the contradiction between speeds and resource utilizations based on FPGA.