Substrate noise coupling in SoC design: Modeling, avoidance, and validation

被引：82

作者：

Afzali-Kusha, Ali ^{[1
]}

Nagata, Makoto

Verghese, Nishath K.

Allstot, David J.

机构：

[1] Univ Tehran, Sch Elect & Comp Engn, Nanoelect Ctr Excellence, Tehran 14395515, Iran

[2] Kobe Univ, Dept Comp & Syst Engn, Kobe, Hyogo 6578501, Japan

[3] Clear Shape Technol, Santa Clara, CA 95054 USA

[4] Univ Washington, Dept Elect Engn, Seattle, WA 98195 USA

来源：

PROCEEDINGS OF THE IEEE | 2006年 / 94卷 / 12期

基金：

美国国家科学基金会;

关键词：

boundary element methods; digital switching noise; finite-difference methods; integrated circuit noise; mixed analog-digital integrated circuits; network reduction methods; noise; noise generators; signal integrity; substrate coupling; substrate noise measurement; switching circuits;

D O I：

10.1109/JPROC.2006.886029

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Issues related to substrate noise in system-on-chip design are described including the physical phenomena responsible for its creation, coupling transmission mechanisms and media, parameters affecting coupling strength, and its impact on mixed-signal integrated circuits. Design guidelines and best practices to minimize the generation, transmission, and reception of substrate noise are outlined, and different modeling approaches and computer simulation methods used in quantifying the noise coupling phenomena are presented. Finally, experiments that validate the modeling approaches and mitigation techniques are reviewed.

引用

页码：2109 / 2138

页数：30

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