Substrate noise coupling in SoC design: Modeling, avoidance, and validation

被引：82

作者：

Afzali-Kusha, Ali ^{[1
]}

Nagata, Makoto

Verghese, Nishath K.

Allstot, David J.

机构：

[1] Univ Tehran, Sch Elect & Comp Engn, Nanoelect Ctr Excellence, Tehran 14395515, Iran

[2] Kobe Univ, Dept Comp & Syst Engn, Kobe, Hyogo 6578501, Japan

[3] Clear Shape Technol, Santa Clara, CA 95054 USA

[4] Univ Washington, Dept Elect Engn, Seattle, WA 98195 USA

来源：

PROCEEDINGS OF THE IEEE | 2006年 / 94卷 / 12期

基金：

美国国家科学基金会;

关键词：

boundary element methods; digital switching noise; finite-difference methods; integrated circuit noise; mixed analog-digital integrated circuits; network reduction methods; noise; noise generators; signal integrity; substrate coupling; substrate noise measurement; switching circuits;

D O I：

10.1109/JPROC.2006.886029

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Issues related to substrate noise in system-on-chip design are described including the physical phenomena responsible for its creation, coupling transmission mechanisms and media, parameters affecting coupling strength, and its impact on mixed-signal integrated circuits. Design guidelines and best practices to minimize the generation, transmission, and reception of substrate noise are outlined, and different modeling approaches and computer simulation methods used in quantifying the noise coupling phenomena are presented. Finally, experiments that validate the modeling approaches and mitigation techniques are reviewed.

引用

页码：2109 / 2138

页数：30

共 130 条

[1] FOLDED SOURCE-COUPLED LOGIC VS CMOS STATIC LOGIC FOR LOW-NOISE MIXED-SIGNAL ICS [J].

ALLSTOT, DJ ;

CHEE, SH ;

KIAEI, S ;

SHRIVASTAWA, M .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS, 1993, 40 (09) :553-563

[2] Experimental comparison of substrate noise coupling using different wafer types [J].

Aragonès, X ;

Rubio, A .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1999, 34 (10) :1405-1409

[3] ANALYSIS AND MODELING OF PARASITIC SUBSTRATE COUPLING IN CMOS CIRCUITS [J].

ARAGONES, X ;

MOLL, F ;

ROCA, M ;

RUBIO, A .

IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 1995, 142 (05) :307-312

[4] SWAN: High-level simulation methodology for digital substrate noise generation [J].

Badaroglu, M ;

Van der Plas, G ;

Wambacq, P ;

Donnay, S ;

Gielen, GGE ;

De Man, HJ .

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2006, 14 (01) :23-33

[5] Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits [J].

Badaroglu, M ;

van Heijningen, M ;

Gravot, V ;

Compiet, J ;

Donnay, S ;

Gielen, GGE ;

De Man, HJ .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2002, 37 (11) :1383-1395

[6]

Basedau P, 1995, 1995 SYMPOSIUM ON VLSI CIRCUITS, P41, DOI 10.1109/VLSIC.1995.520679

[7] Substrate noise modeling in early floorplanning of MS-SOCs [J].

Blakiewicz, Grzegorz ;

Jeske, Marcin ;

Chrzanowska-Jeske, Malgorzata ;

Zhang, Jin S. .

ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2005, :819-823

[8]

BLALACK T, 1995, ISSCC DIG TECH PAP I, V38, P200, DOI 10.1109/ISSCC.1995.535522

[9] SubCALM: A program for hierarchical substrate coupling simulation on floorplan level [J].

Brandtner, T ;

Weigel, R .

DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2004, :616-621

[10] Principles of substrate crosstalk generation in CMOS circuits [J].

Briaire, J ;

Krisch, KS .

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2000, 19 (06) :645-653

← 1 2 3 4 5 6 7 8 9 10 →