Quantitative analysis of errors in on-wafer s-parameter de-embedding techniques for high frequency device modeling

The de-embedding of intrinsic device parameters from on-wafer measurements is a central problem in high frequency device measurement and modeling. The first quantitative analysis of the errors associated with de-embedding on-wafer s-parameter measurements of 90nm bulk FETs and 130mn SiGe HBTs taking into account the effects of non-ideal standards is presented. Four different on-wafer deembedding techniques are examined. Electromagnetic (E-M) simulations accounting for these non-idealities are used to compare different methods. It is demonstrated that unwanted parasitics in standards can significantly affect parameters extracted using more complex deembedding techniques. The most sensitive standard is identified and an optimized design is presented.