共 28 条
[1]
AUSTING RM, 1999, MICRO 32 P, P196
[2]
Defect and error tolerance in the presence of massive numbers of defects
[J].
IEEE DESIGN & TEST OF COMPUTERS,
2004, 21 (03)
:216-227
[4]
Chatelain P, 2000, Endocr Regul, V34, P33
[5]
Analysis and testing for error tolerant motion estimation
[J].
DFT 2005: 20TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS,
2005,
:514-522
[6]
Frangiotti M, 1995, PROCEEDINGS OF THE EIGHTH INTERNATIONAL KANT CONGRESS, VOL II, PT 1, SECT 1-9, P207, DOI 10.1109/DFTVS.1995.476954
[7]
Impact of CMOS process scaling and SOI on the soft error rates of logic processes
[J].
2001 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS,
2001,
:73-74
[8]
Hennessy JL, 2019, COMPUTER ARCHITECTUR
[9]
Johnson B., 1989, Design and Analysis of Fault-Tolerant Digital Systems
[10]
LU DJ, 1982, IEEE T COMPUT, V31, P681, DOI 10.1109/TC.1982.1676066