Small Delay Fault Model for Intra-Gate Resistive Open Defects

被引：10

作者：

Arai, Masayuki ^{[1
]}

Suto, Akifumi ^{[1
]}

Iwasaki, Kazuhiko ^{[1
]}

Nakano, Katsuyuki ^{[2
]}

Shintani, Michihiro ^{[2
]}

Hatayama, Kazumi ^{[2
]}

Aikyo, Takashi ^{[2
]}

机构：

[1] Tokyo Metropolitan Univ, Fac Syst Design, Tokyo 1910065, Japan

[2] Semiconduct Technol Acad Res Ctr STARC, Yokohama, Kanagawa 222, Japan

来源：

2009 27TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS | 2009年

关键词：

D O I：

10.1109/VTS.2009.25

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We propose the fault model considering weak resistive opens inside the gate which might cause pattern-sequence-dependent and timing-dependent malfunction of the circuit. We assume the fixed observation interval for the signal transition, and derive the minimum resistance of intra-gate resistive opens to be detected as a fault by SPICE simulation. Based on the simulation results, we establish three fault models, that is, the one considering the location of the resistance, the one considering both the location and the resistance distribution, and the simplified one where str and stf faults considering the signal transition of the input ports are assumed The coverage calculation for the primitive gates and small benchmark circuit reveals that the proposed models have more accuracy on the detection of weak open defects.

引用

页码：27 / +

页数：2