Minimally buffered deflection router for spiking neural network hardware implementations

被引:4
作者
Liu, Junxiu [1 ]
Jiang, Dong [1 ]
Luo, Yuling [1 ,2 ]
Qiu, Senhui [1 ,3 ]
Huang, Yongchuang [1 ]
机构
[1] Guangxi Normal Univ, Sch Elect Engn, Guilin, Peoples R China
[2] Guangxi Normal Univ, Guangxi Key Lab Multisource Informat Min & Secur, Guilin, Peoples R China
[3] Guangxi Key Lab Wireless Wideband Commun & Signal, Guilin, Peoples R China
基金
中国国家自然科学基金;
关键词
Spiking neural networks; Neuromorphic computing; Networks-on-chip; Deflection routers; ON-CHIP; SPINNAKER; NOC;
D O I
10.1007/s00521-021-05817-x
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
Spiking neural networks (SNNs) have the potential to closely mimic the information processing of biological brains, by using massive neurons that are interconnected in a complex network. Recent researches have considered using electronic hardware circuits to SNN implementations to meet real-time processing requirements. Network-on-Chips (NoCs) have been widely used to develop such SNN circuits as their interconnections can offer stable interconnectivity for neuron communications with high throughput and real-time execution. However, its scalability is limited due to expensive and complex NoC routers which leads to high energy consumption and large area utilization. Therefore, a minimally buffered deflection router (MBDR) is proposed in this work to address the scalability challenge of the hardware SNNs. It employs a deflection router technique to remove most of the inter-buffers and other expensive components of the conventional routers. Moreover, a novel flow controller is developed in MBDR to further reduce power consumption. Compared to existing approaches, experimental results show that based on 90-nm CMOS technology the area and power consumption of the proposed router are reduced by similar to 86% and similar to 88%, respectively. In the meantime, system throughput is maintained at a high level.
引用
收藏
页码:11753 / 11764
页数:12
相关论文
共 35 条
[1]   True North: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip [J].
Akopyan, Filipp ;
Sawada, Jun ;
Cassidy, Andrew ;
Alvarez-Icaza, Rodrigo ;
Arthur, John ;
Merolla, Paul ;
Imam, Nabil ;
Nakamura, Yutaka ;
Datta, Pallab ;
Nam, Gi-Joon ;
Taba, Brian ;
Beakes, Michael ;
Brezzo, Bernard ;
Kuang, Jente B. ;
Manohar, Rajit ;
Risk, William P. ;
Jackson, Bryan ;
Modha, Dharmendra S. .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2015, 34 (10) :1537-1557
[2]   Routerless Networks-on-Chip [J].
Alazemi, Fawaz ;
Azizimazreah, Arash ;
Bose, Bella ;
Chen, Lizhong .
2018 24TH IEEE INTERNATIONAL SYMPOSIUM ON HIGH PERFORMANCE COMPUTER ARCHITECTURE (HPCA), 2018, :492-503
[3]   Networks on chips: A new SoC paradigm [J].
Benini, L ;
De Micheli, G .
COMPUTER, 2002, 35 (01) :70-+
[4]   Scalable Hierarchical Network-on-Chip Architecture for Spiking Neural Network Hardware Implementations [J].
Carrillo, Snaider ;
Harkin, Jim ;
McDaid, Liam J. ;
Morgan, Fearghal ;
Pande, Sandeep ;
Cawley, Seamus ;
McGinley, Brian .
IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 2013, 24 (12) :2451-2461
[5]   Advancing interconnect density for spiking neural network hardware implementations using traffic-aware adaptive network-on-chip routers [J].
Carrillo, Snaider ;
Harkin, Jim ;
McDaid, Liam ;
Pande, Sandeep ;
Cawley, Seamus ;
McGinley, Brian ;
Morgan, Fearghal .
NEURAL NETWORKS, 2012, 33 :42-57
[6]  
Dang Khanh N., 2019, 2019 International Conference on Internet of Things, Embedded Systems and Communications (IINTEC). Proceedings, P155, DOI 10.1109/IINTEC48298.2019.9112123
[7]   A world survey of artificial brain projects, Part I Large-scale brain simulations [J].
de Garis, Hugo ;
Chen Shuo ;
Goertzel, Ben ;
Lian Ruiting .
NEUROCOMPUTING, 2010, 74 (1-3) :3-29
[8]  
Fallin C., 2012, NOCS, P1
[9]  
Fallin C, 2011, INT S HIGH PERF COMP, P144, DOI 10.1109/HPCA.2011.5749724
[10]   Addressing Transient and Permanent Faults in NoC With Efficient Fault-Tolerant Deflection Router [J].
Feng, Chaochao ;
Lu, Zhonghai ;
Jantsch, Axel ;
Zhang, Minxuan ;
Xing, Zuocheng .
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2013, 21 (06) :1053-1066