Redundant Via Insertion Based on SCA

被引：0

作者：

Wang, Jun-Ping ^{[1
]}

Xing, Run-Sen ^{[1
]}

Xu, Dan ^{[1
]}

Su, Yong-Bang ^{[1
]}

Feng, Rui-Ping ^{[1
]}

Wei, Rong ^{[1
]}

Li, Ya-Ning ^{[1
]}

Zhao, Teng-Wei ^{[1
]}

机构：

[1] Xidian Univ, Sch Telecommun Engn, Xian 710071, Peoples R China

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2016年 / 24卷 / 02期

基金：

中国国家自然科学基金;

关键词：

Candidate range; integrated circuit (IC); redundant via (RV) insertion; short critical area (SCA); DESIGN;

D O I：

10.1109/TVLSI.2015.2416065

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The redundant via (RV) insertion is a widely used technique to enhance chip reliability. However, inserting an RV adjacent to a single via (SV) may create extra critical area (CA) between nets and worsen the circuit's yield. In this paper, we present a short CA (SCA)-constrained RV insertion method for yield optimization with a consideration of the SCA. First, we find the candidate ranges of the SVs, judge whether they can be inserted by RVs, and set the values of their corresponding direction marks and weight. Then, we update the direction marks and the weight of the candidate ranges. Finally, according to the direction marks and the weight of the candidate ranges, we determine the optimization sequence of the candidate ranges and complete the insertion of the RVs. The simulation results show that our method can get a high insertion rate and a good control of the incremental SCA between nets for yield.

引用

页码：720 / 728

页数：9

共 27 条

[1] Targeted layout modifications for semiconductor yield/reliability enhancement [J].

Allan, GA .

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 2004, 17 (04) :573-581

[2]

[Anonymous], REF FLOW 9 0

[3] Product yield prediction system and critical area database [J].

Barnett, Thomas S. ;

Bickford, Jeanne P. ;

Weger, Alan J. .

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 2008, 21 (03) :337-341

[4] Enhanced Redundant Via Insertion with Multi-Via Mechanisms [J].

Chang, Ting-Feng ;

Kan, Tsang-Chi ;

Yang, Shih-Hsien ;

Ruan, Shanq-Jang .

2011 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI), 2011, :218-223

[5] Full-chip routing considering double-via insertion [J].

Chen, Huang-Yu ;

Chiang, Mei-Fang ;

Chang, Yao-Wen ;

Chen, Lumdo ;

Han, Brian .

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2008, 27 (05) :844-857

[6]

Chiang C, 2006, 2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, P1099

[7] Track routing and optimization for yield [J].

Cho, Minsik ;

Xiang, Hua ;

Puri, Ruchir ;

Pan, David Z. .

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2008, 27 (05) :872-882

[8] In-line methodology for defectivity analysis from dark field wafer inspection to defect root cause analysis using FIB cut [J].

Ducotey, Gregoire ;

Couvrat, Alexandre ;

Audran, Veronique ;

Pepper, David ;

Couturier, Laurent ;

David, Denis .

2008 IEEE/SEMI ADVANCED SEMICONDUCTOR MANUFACTURING CONFERENCE, 2008, :138-141

[9]

Gopalani Salman, 2009, 2009 12th International Symposium on Integrated Circuits (ISIC 2009), P29

[10]

Gupta P, 2003, ICCAD-2003: IEEE/ACM DIGEST OF TECHNICAL PAPERS, P681

← 1 2 3 →