Design and Realization of High Speed Digital Visual Signal Receiver

A digital visual interface receiver solution which used a new kind of clock and data recovery circuit is designed, implemented the 10bits data recovery by a elastic buffer inserted between the oversampler and DPLL, increased the correct rate of decision. The change of VCO frequency caused by the control voltage ripple and the clock jitter are reduced through the improved V to I circuit that can get a low gain of VCO in PLL. The input clock can be automatic detected and divided into three segment, fulfilled the high frequency capture range. The receiver is fabricated by SMIC 0.18um CMOS process, test result meet the requirements of DVI Specification.