Impact of device scaling on the electrical properties of MoS2 field-effect transistors

被引:48
作者
Arutchelvan, Goutham [1 ,2 ]
Smets, Quentin [1 ]
Verreck, Devin [1 ]
Ahmed, Zubair [1 ]
Gaur, Abhinav [2 ]
Sutar, Surajit [1 ]
Jussot, Julien [1 ]
Groven, Benjamin [1 ]
Heyns, Marc [1 ,2 ]
Lin, Dennis [1 ]
Asselberghs, Inge [1 ]
Radu, Iuliana [1 ]
机构
[1] IMEC, Leuven, Belgium
[2] Katholieke Univ Leuven, Leuven, Belgium
关键词
D O I
10.1038/s41598-021-85968-y
中图分类号
O [数理科学和化学]; P [天文学、地球科学]; Q [生物科学]; N [自然科学总论];
学科分类号
07 ; 0710 ; 09 ;
摘要
Two-dimensional semiconducting materials are considered as ideal candidates for ultimate device scaling. However, a systematic study on the performance and variability impact of scaling the different device dimensions is still lacking. Here we investigate the scaling behavior across 1300 devices fabricated on large-area grown MoS2 material with channel length down to 30 nm, contact length down to 13 nm and capacitive effective oxide thickness (CET) down to 1.9 nm. These devices show best-in-class performance with transconductance of 185 mu S/mu m and a minimum subthreshold swing (SS) of 86 mV/dec. We find that scaling the top-contact length has no impact on the contact resistance and electrostatics of three monolayers MoS2 transistors, because edge injection is dominant. Further, we identify that SS degradation occurs at short channel length and can be mitigated by reducing the CET and lowering the Schottky barrier height. Finally, using a power performance area (PPA) analysis, we present a roadmap of material improvements to make 2D devices competitive with silicon gate-all-around devices.
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页数:11
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