Measurement-based method to characterize parasitic parameters of the integrated power electronics modules

被引:62
作者
Yang, Liyu [1 ]
Odendaal, Willem G. Hardus
机构
[1] N Carolina State Univ, Semicond Power Elect Ctr, Raleigh, NC 27695 USA
[2] Virginia Polytech Inst & State Univ, Bradley Dept Elect & Comp Engn, Natl Sci Fdn, Engn Res Ctr Power Elect Syst, Blacksburg, VA 24061 USA
基金
欧洲研究理事会; 美国国家科学基金会;
关键词
characterization; common-mode (CM); differential mode (DM); electromagnetic compatibility (EMC); electromagnetic interference (EMI); integrated power electronics modules (IPEMs); measurement; noise; packaging; parasitic capacitance; parasitic inductors;
D O I
10.1109/TPEL.2006.886615
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A measurement-based method for extracting the parasitic parameters of active power electronics modules (IPEMs) is proposed. Parasitic inductances and capacitances inside the IPEM can all be extracted using this method without destroying the structure. The linearized model is derived from impedance measurement and it is valid from low frequency to frequencies as high as 100 MHz. Extracted parameters are compared to those from commercial software and the results are in good agreement. A parallel resonance method is proposed for the characterization of commonmode capacitances.
引用
收藏
页码:54 / 62
页数:9
相关论文
共 15 条
  • [1] [Anonymous], P IEEE INT S EMC MON
  • [2] Integrated electrical and thermal modeling and analysis of IPEMs
    Chen, JZ
    Wu, YX
    Borojevich, DS
    Bohn, JH
    [J]. COMPEL 2000: 7TH WORKSHOP ON COMPUTERS IN POWER ELECTRONICS, PROCEEDINGS, 2000, : 24 - 27
  • [3] Dai N., 1996, P PESC 96 BAV IT JUN, V2, P1370
  • [4] Gutsmann B, 2000, IEEE POWER ELECTRON, P1291, DOI 10.1109/PESC.2000.880496
  • [5] LIANG Z, 2001, P 16 ANN IEEE APPL P, V2, P1057
  • [6] LU GQ, 2000, PESC, V3, P1261
  • [7] McShane E., 2000, IWIPP 2000. International Workshop on Integrated Power Packaging (Cat. No.00EX426), P55, DOI 10.1109/IWIPP.2000.885182
  • [8] TEULINGS W, 1997, PESC 997 REC 28 IEEE, V2, P1516
  • [9] Parasitic extraction methodology for insulated gate bipolar transistors
    Trivedi, M
    Shenai, K
    [J]. IEEE TRANSACTIONS ON POWER ELECTRONICS, 2000, 15 (04) : 799 - 804
  • [10] van Wyk J. D., 1999, P CTR POW EL SYST C, P61