A Low-Noise Wideband Digital Phase-Locked Loop Based on a Coarse-Fine Time-to-Digital Converter With Subpicosecond Resolution

被引：85
作者：
Lee, Minjae [1 ]
Heidari, Mohammad E. [2 ]
Abidi, Asad A. [3 ]
机构：
[1] Agilent Technol, Santa Clara, CA 95051 USA
[2] Broadcom Corp, San Diego, CA 92127 USA
[3] Univ Calif Los Angeles, Dept Elect Engn, Los Angeles, CA 90095 USA
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2009年 / 44卷 / 10期
关键词：
Coarse-fine architecture; digital phase-locked loop; time amplifier; time-to-digital converter (TDC); wideband modulation; FREQUENCY-SYNTHESIZER; CMOS; PLL;
D O I：
10.1109/JSSC.2009.2028753
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents the design of a digital PLL which uses a high-resolution time-to-digital converter (TDC) for wide loop bandwidth. The TDC uses a time amplification technique to reduce the quantization noise down to less than 1 ps root mean square (RMS). Additionally TDC input commutation reduces low-frequency spurs due to inaccurate TDC scaling factor in a counter-assisted digital PLL. The loop bandwidth is set to 400 kHz with a 25 MHz reference. The in-band phase noise contribution from the TDC is -116 dBc/Hz, the phase noise is -117 dBc/Hz at high band (1.8 GHz band) 400 kHz offset, and the RMS phase error is 0.3 degrees
引用
收藏
页码：2808 / 2816
页数：9
相关论文
共 17 条
[1]  
[Anonymous], 2006, ALL DIGITAL FREQUENC
[2]  
HEIDARI ME, 2008, P S VLSI CIRC JUN, P98
[3]   All-Digital Outphasing Modulator for a Software-Defined Transmitter [J].
Heidari, Mohammad E. ;
Lee, Minjae ;
Abidi, Asad A. .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2009, 44 (04) :1260-1271
[4]   A Low-Noise Wide-BW 3.6-GHz Digital ΔΣ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation [J].
Hsu, Chun-Ming ;
Straayer, Matthew Z. ;
Perrott, Michael H. .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2008, 43 (12) :2776-2786
[5]   A 9b, 1.25ps resolution coarse-fine time-to-digital converter in 90nm CMOS that amplifies a time residue [J].
Lee, Miniae ;
Abidi, Asad A. .
2007 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2007, :168-169
[6]   A low noise, wideband digital phase-locked loop based on a new Time-to-Digital Converter with subpicosecond resolution [J].
Lee, Minjae ;
Heidari, Mohammad E. ;
Abidi, Asad A. .
2008 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2008, :112-113
[7]   A 9b, 1.25 ps resolution coarse-fine time-to-digital converter in 90 nm CMOS that amplifies a time residue [J].
Lee, Minjae ;
Abidi, Asad A. .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2008, 43 (04) :769-777
[8]   A 1-MHZ bandwidth 3.6-GHz 0.18-μm CMOS fractional-N synthesizer utilizing a hybrid PFD/DAC structure for reduced broadband phase noise [J].
Meninger, SE ;
Perrott, MH .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2006, 41 (04) :966-980
[9]   A wideband 2.4-GHz delta-sigma fractional-N PLL with 1-MB/s in-loop modulation [J].
Pamarti, S ;
Jansson, L ;
Galton, I .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2004, 39 (01) :49-62
[10]   All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS [J].
Staszewski, RB ;
Muhammad, K ;
Leipold, D ;
Hung, CM ;
Ho, YC ;
Wallberg, JL ;
Fernando, C ;
Maggio, K ;
Staszewski, R ;
Jung, T ;
Koh, J ;
John, S ;
Deng, IY ;
Sarda, V ;
Moreira-Tamayo, O ;
Mayega, V ;
Katz, R ;
Friedman, O ;
Eliezer, OE ;
De-Obaldia, E ;
Balsara, PT .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2004, 39 (12) :2278-2291
12