Improvement of conduction in 3-D NAND memory devices by channel and junction optimization

被引：11

作者：

Arreghini, Antonio ^{[1
]}

Banerjee, Kaustuv ^{[1
]}

Verreck, Devin ^{[1
]}

Palayam, Senthil Vadakupudhu ^{[1
]}

Rosseel, Erik ^{[1
]}

Nyns, Laura ^{[1
]}

Van den Bosch, Geert ^{[1
]}

Furnemont, Arnaud ^{[1
]}

机构：

[1] IMEC, Kapeldreef 75, B-3001 Leuven, Belgium

来源：

2019 IEEE 11TH INTERNATIONAL MEMORY WORKSHOP (IMW 2019) | 2019年

关键词：

INTEGRATION;

D O I：

10.1109/imw.2019.8739661

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We explore different ways to improve the quality of polysilicon channel in 3-D NAND flash devices to increase the current conduction. The analysis includes the formation of the device bottom junction ( benchmarking diffused vs. epitaxially grown source), the role of defect passivation, the role of the protection layer on channel crystallization and the impact of macaroni channel thickness on grain size and on transistor performance.

引用

页码：140 / 143

页数：4

共 11 条

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