Chain: A delay-insensitive chip area interconnect

被引：144

作者：

Bainbridge, J ^{[1
]}

Furber, S ^{[1
]}

机构：

[1] Univ Manchester, Dept Comp Sci, Manchester M13 9PL, Lancs, England

来源：

IEEE MICRO | 2002年 / 22卷 / 05期

基金：

英国工程与自然科学研究理事会;

关键词：

D O I：

10.1109/MM.2002.1044296

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The increasing complexity of system-on-a-chip designs exposes the limits imposed by the standard synchronous bus. The authors propose a mixed system as a solution.

引用

页码：16 / 23

页数：8

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