Low-complexity block-based motion estimation via one-bit transforms

被引：174
作者：
Natarajan, B
Bhaskaran, V
Konstantinides, I
机构：
[1] Hewlett-Packard Laboratories, Palo Alto
来源：
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY | 1997年 / 7卷 / 04期
关键词：
architectures; CPU performance instructions; motion estimation; multimedia; video compression standards;
D O I：
10.1109/76.611181
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
We present an algorithm and a hardware architecture for block-based motion estimation that involves transforming video sequences from a multibit to a one-bit/pixel representation and then applying conventional motion estimation search strategies, This results in substantial reductions in arithmetic and hardware complexity and reduced power consumption, while maintaining good compression performance. Experimental results and a custom hardware design using a linear array of processing elements are also presented.
引用
收藏
页码：702 / 706
页数：5
相关论文
共 7 条
  • [1] Bhaskaran V., 1995, IMAGE VIDEO COMPRESS
  • [2] FENG J, 1995, IEEE INT C IM PROC W, P496
  • [3] BLOCKMATCHING MOTION ESTIMATION ALGORITHMS - NEW RESULTS
    GHARAVI, H
    MILLS, M
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1990, 37 (05): : 649 - 651
  • [4] MIZUKI M, 1996, IEEE ICASSP 96, V6, P3248
  • [5] Rao K. R., 2014, Discrete cosine transform: algorithms, advantages, applications
  • [6] *TEL RES, H263 TEL RES
  • [7] A FAMILY OF VLSI DESIGNS FOR THE MOTION COMPENSATION BLOCK-MATCHING ALGORITHM
    YANG, KM
    SUN, MT
    WU, L
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1989, 36 (10): : 1317 - 1325
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