A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration

被引:206
作者
Jamal, SM [1 ]
Fu, DH
Chang, NCJ
Hurst, PJ
Lewis, SH
机构
[1] Marvell Semicond, Sunnyvale, CA 94086 USA
[2] Univ Calif Davis, Dept Elect & Comp Engn, Solid State Circuits Res Lab, Davis, CA 95616 USA
关键词
adaptive systems; analog-to-digital conversion; calibration; CMOS analog integrated circuits;
D O I
10.1109/JSSC.2002.804327
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Digital calibration using adaptive signal processing corrects for offset mismatch, gain mismatch, and sample-time error between time-interleaved channels in a 10-b 120-Msample/s pipelined analog-to-digital converter (ADC). Offset mismatch between channels is overcome with a random chopper-based offset calibration. Gain mismatch and sample-time error are overcome with correlation-based algorithms, which drive the correlation between a signal and its chopped image or its chopped and delayed image to zero. Test results show that, with a 0.99-MHz sinusoidal input, the ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 56.8 dB, a peak integral nonlinearity of 0.88 least significant bit (LSB), and a peak differential nonlinearity of 0.44 LSB. For a 39.9-MHz sinusoidal input, the ADC achieves a peak SNDR of 50.2 dB. The active area is 5.2 mm(2), and the power dissipation is 234 mW from a 3.3-V supply.
引用
收藏
页码:1618 / 1627
页数:10
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