A CMOS 15-bit 125-MS/s time-interleaved ADC with digital background. calibration

被引：4

作者：

Lee, Zwei-Mei ^{[1
]}

Wang, Cheng-Yeh ^{[1
]}

Wu, Jieh-Tsorng ^{[1
]}

机构：

[1] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu 300, Taiwan

来源：

PROCEEDINGS OF THE IEEE 2006 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2006年

关键词：

D O I：

10.1109/CICC.2006.320912

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 15-bit 125-MS/s two-channel time-interleaved pipelined ADC is fabricated in a 0.18 mu m CMOS technology, and achieves 91.9 dB SFDR, 69.9 dB SNDR for a 9.99 MHz input. The ADC uses a single sample-and-hold amplifier which employs a precharging circuit technique to mitigate the performance requirements for its opamp. Digital background calibration is applied to maintain the conversion linearity of each AID channel and also correct both gain and offset mismatches between the two channels. Excluding I/O buffers, the chip occupies an area of 4.3 x 4.3 mm(2) and dissipates 909 mW from a 1.8 V supply.

引用

页码：209 / 212

页数：4

共 6 条

[1] ALI AM, 2005, IEEE CUST INT CIRC C
[2] BOGNER P, 2006, IEEE INT SOL STAT CI, P224
[3] Hakkarainen V, 2004, 22ND NORCHIP CONFERENCE, PROCEEDINGS, P171
[4] Hsu CC, 2003, IEICE T ELECTRON, VE86C, P2122
[5] A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration
Jamal, SM
Fu, DH
Chang, NCJ
Hurst, PJ
Lewis, SH
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2002, 37 (12) : 1618 - 1627
[6] A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration
Liu, HC
Lee, ZM
Wu, JT
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2005, 40 (05) : 1047 - 1056

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