A fast modular exponentiation for RSA on systolic arrays

This paper presents two systolic algorithms for modular exponentiations based on a k-SR representation. In a systolic k-SR scheme, throughput is one modular exponentiation of a message block having n digits in every clock cycle, with a latency of nearly 5n/4 cycles to output the final result. The speedup for a group of messages having l message blocks is around (5/6l + 2/3n), compared to a single processor or processing element for modular multiplications. The scheme saves nearly n/4 processing elements and around n/4 modular multiplications, compared with the scheme in [23].