Exploiting instruction- and data-level parallelism

被引：15

作者：

Espasa, R

Valero, M

机构：

[1] Polytech. University of Catalunya, Barcelona

[2] Computer Architecture Department, Polytech. University of Catalunya, Barcelona

[3] Campus Nord, C6-E202, Dept. Arquitectura Computadors, Univ. Politecnica de Catalunya, 08034 Barcelona, Gran Capita S/N

来源：

IEEE MICRO | 1997年 / 17卷 / 05期

关键词：

D O I：

10.1109/40.621210

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Simultaneous multithreaded vector architectures combine the best of data-level and instruction-level parallelism and perform better than either approach could separately. Our design achieves performance equivalent to executing 15 to 26 scalar instructions/cycle for numerical applications.

引用

页码：20 / 27

页数：8

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