Design and implementation of modified BCD digit multiplier for digit-by-digit decimal multiplier

Decimal multiplication is the most common operation in arithmetic applications. This paper presents an area-efficient digit-by-digit decimal multiplier using a modified binary-coded decimal digit multiplier. In general, a Binary-Coded Decimal (BCD) digit multiplier consists of two kinds of block, namely binary multiplier, and Partial Product Binary-to-Decimal (PPBD) converter. In the BCD digit multiplier design, the binary multiplier produces the partial product output by multiplying the multiplier value along with multiplicand, and the PPBD converter used to convert the binary partial product into the decimal value. Instead of the binary multiplier, this paper proposes a constant multiplier design to generate binary partial product values. Here, the multiplier value considers as the constant value. Further, the proposed architectures design and implement using both Field-Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC). When compared with the existing methods, the implementation results show that the proposed design effectively reduces the area requirement and delay.