ASIC Implementation of Linear Equalizer Using Adaptive FIR Filter

被引:10
作者
Jyothi, Grande Naga [1 ]
Gorantla, Anusha [2 ]
Kudithi, Thirumalesu [1 ]
机构
[1] Vellore Inst Technol, Vellore, Tamil Nadu, India
[2] Qis Coll Engn & Technol, Vegamukkapalem, Andhra Pradesh, India
关键词
Equalizer; FIR Filter; LMS Adaptive Filter; MAC; Segmented Block; LOW-POWER; OPTIMIZATION;
D O I
10.4018/IJeC.2020100105
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Power consumption plays a crucial role in the design of portable wireless communication devices, as it has a direct influence on the battery weight and volume required for operation. This article presents a novel design for a linear LMS equalizer for the optimization of filter order. The article describes the use of a variable length algorithm for dynamically updating the tap-length of the LMS adaptive filter to optimize the performance and for reducing the power in the adaptive filter core. An algorithm is applied to reduce and adjust the order of the filter in linear equalizer according to the channel conditions. The proposed design is implemented in the synopsis TSMC 65nm technology. The results from using the algorithm uses 28% less power when compared with the conventional 64-tap fixed length adaptive filter design. It has also been shown that the low-complexity of the additional circuitry needed for the variable length adaptive filter presents minimal overhead for this architecture.
引用
收藏
页码:59 / 71
页数:13
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