Optimizing quarter and sub-quarter micron CMOS circuit speed considering interconnect loading effects

被引：3

作者：

Chen, K ^{[1
]}

Hu, CM ^{[1
]}

Fang, P ^{[1
]}

Lin, MR ^{[1
]}

Wollesen, DL ^{[1
]}

机构：

[1] ADV MICRO DEVICES INC, SUNNYVALE, CA 94088 USA

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 1997年 / 44卷 / 09期

关键词：

D O I：

10.1109/16.622616

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An experimentally confirmed accurate CMOS gate delay model is applied to the CMOS sing oscillators with interconnect loading. The optimum gate oxide thickness T-ox should he chosen differently as interconnect loading varies. Guidelines in choosing optimum T-ox for different interconnect Loading, combined with channel length and power supply scaling, are obtained.

引用

页码：1556 / 1558

页数：3

共 6 条

[1]

Bohr MT, 1996, SOLID STATE TECHNOL, V39, P105

[2] The impact of device scaling and power supply change on CMOS gate performance [J].