A 2.4 GHz Low-Power Sixth-Order RF Bandpass ΔΣ Converter in CMOS

被引：41

作者：

Ryckaert, Julien ^{[1
]}

Borremans, Jonathan ^{[1
]}

Verbruggen, Bob ^{[1
,2
]}

Bos, Lynn ^{[1
,2
]}

Armiento, Costantino ^{[1
,3
]}

Craninckx, Jan ^{[1
]}

Van der Plas, Geert ^{[1
]}

机构：

[1] IMEC, Leuven, Belgium

[2] Univ Brussels VUB, Brussels, Belgium

[3] Univ Pisa, Pisa, Italy

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2009年 / 44卷 / 11期

关键词：

Analog-to-digital converters; continuous-time Delta Sigma modulation; direct RF sampling; impulse-invariance transformation; ADC; MODULATOR; DESIGN;

D O I：

10.1109/JSSC.2009.2028914

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A sixth-order RF bandpass Delta Sigma ADC operating on the 2.4 GHz ISM band, which is suitable for RF digitization is presented. The bandpass loop filter is based on digitally programmable Gm-LC resonators that can be calibrated online to adjust the RF center frequency. By sampling below the input Nyquist frequency, the clock in the system was reduced to 3 GHz, allowing a large reduction of the power consumption. Implemented in a standard 90 nm CMOS process, the IC achieves 40 dB and 62 dB of SNDR and SFDR, respectively, on a 60 MHz bandwidth with 40 mW of power consumption leading to a FoM of 245 GHz/W (4.1 pJ/conversion step). This implementation paves a possible way towards direct RF digitization receiver architectures.

引用

页码：2873 / 2880

页数：8

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