Floating-Point Fused Multiply-Add under HUB Format

被引：0
|
作者：
Hormigo, Javier [1 ]
Villalba-Moreno, Julio [1 ]
Gonzalez-Navarro, Sonia [1 ]
机构：
[1] Univ Malaga, Dept Comp Architecture, Andalucia Tech, Malaga, Spain
来源：
2020 IEEE 27TH SYMPOSIUM ON COMPUTER ARITHMETIC (ARITH) | 2020年
关键词：
Fused multiplication-addition; HUB format; DSP applications; Deep-learning;
D O I：
10.1109/ARITH48897.2020.00010
中图分类号：
TP39 [计算机的应用];
学科分类号：
081203 ; 0835 ;
摘要：
The Half-Unit-Biased (HUB) format has interesting advantages for implementing floating-point arithmetic which has been proved for the four basic arithmetic operations as well as square root. Nevertheless, although Floating-point Fused Multiply-add (FMA) operation (AxB + C) is one of the most important and complex arithmetic instructions in modern processors, FMA operation for HUB numbers has not been confronted yet. In this paper, we present a design to deal with this operation under HUB format. The key points to turn the conventional FMA architecture into a HUB unit are explained. Comparing the ASIC implementation of a HUB FMA unit with the conventional one, the former reduces the required area and power up to 38% and 35%, respectively, for single-precision. For BFloat16, the HUB FMA increases the speed a 15%, and even then, reduces the area and power by 26% and 12%, respectively.
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页码：1 / 8
页数：8
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