Fully Aligned Via Integration for Extendibility of Interconnects to Beyond the 7 nm Node

被引：0

作者：

Briggs, Benjamin D. ^{[1
]}

Peethala, C. B. ^{[1
]}

Rath, D. L. ^{[2
]}

Lee, J. ^{[1
]}

Nguyen, S. ^{[1
]}

LiCausi, N. V. ^{[4
]}

McLaughlin, P. S. ^{[2
]}

You, H. ^{[4
]}

Sil, D. ^{[1
]}

Lanzillo, N. A. ^{[1
]}

Huang, H. ^{[1
]}

Patlolla, R. ^{[1
]}

Haigh, T., Jr. ^{[1
]}

Xu, Y. ^{[1
]}

Park, C. ^{[4
]}

Kerber, P. ^{[2
]}

Shobha, H. K. ^{[1
]}

Kim, Y. ^{[5
]}

Demarest, J. ^{[1
]}

Li, J. ^{[1
]}

Lian, G. ^{[3
]}

Ali, M. ^{[3
]}

t Le, C. ^{[3
]}

Ryan, E. T. ^{[4
]}

Clevenger, L. A. ^{[1
]}

Canaperi, D. F. ^{[1
]}

Standaert, T. E. ^{[1
]}

Bonilla, G. ^{[1
]}

Huang, E. ^{[1
]}

机构：

[1] IBM Albany Nanotech, 257 Fuller Rd, Albany, NY 12203 USA

[2] IBM TJ Watson Res Ctr, 257 Fuller Rd, Albany, NY 12203 USA

[3] IBM Syst, 257 Fuller Rd, Albany, NY 12203 USA

[4] GLOBALFOUNDRIES Inc, 257 Fuller Rd, Albany, NY 12203 USA

[5] Samsung Elect, 257 Fuller Rd, Albany, NY 12203 USA

来源：

2017 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2017年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A fully aligned via (FAV) integration scheme is introduced and demonstrated at 36 nm metal pitch, with extendibility to beyond the 7 nm node. Selective chemistries were developed to recess Cu and W wires and their associated barrier liner materials, so as to create local topography with no adverse effects on these wiring levels or their dielectrics. Dielectric cap layers were optimized for excellent via RIE selectivity, to act as via guiding structures during subsequent level pattern definition. This combination mitigates via overlay and critical dimension (CD) errors. FAV integration can enable line/via area scaling for 70% lower line resistances and 30% larger via contact areas at the same node. Concurrently, FAV improves TDDB reliability through increased minimum insulator spacing, and EM reliability by maximizing via/wire contact area.

引用

页数：4

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