SP-SOI: A third generation surface potential based compact SOI MOSFET model

被引：0

作者：

Wu, W ^{[1
]}

Li, X ^{[1
]}

Wang, H ^{[1
]}

Gildenblat, G ^{[1
]}

Workman, G ^{[1
]}

Veeraraghavan, S ^{[1
]}

McAndrew, C ^{[1
]}

机构：

[1] Penn State Univ, Dept Elect Engn, University Pk, PA 16802 USA

来源：

CICC: PROCEEDINGS OF THE IEEE 2005 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2005年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We report the first SOI MOSFET model that takes advantage of the recent progress in bulk MOSFET modeling. The surface-potential-based model is implemented without iterative loops, and includes physical modeling of the moderate inversion region and all small-geometry effects without relying on the traditional threshold-voltage-based formulation. The new model is verified for a 90 run node process (40nm polysilicon length) and is implemented in a circuit simulator.

引用

页码：819 / 822

页数：4

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