High performance of junctionless MOSFET with asymmetric gate

被引：14

作者：

Wang, Ying ^{[1
]}

Tang, Yan ^{[2
]}

Sun, Ling-ling ^{[1
]}

Cao, Fei ^{[1
]}

机构：

[1] Hangzhou Dianzi Univ, Key Lab RF Circuits & Syst, Minist Educ, Hangzhou 310018, Zhejiang, Peoples R China

[2] Harbin Engn Univ, Coll Informat & Commun Engn, Harbin 150001, Peoples R China

来源：

SUPERLATTICES AND MICROSTRUCTURES | 2016年 / 97卷

基金：

中国国家自然科学基金; 黑龙江省自然科学基金;

关键词：

Asymmetric gate; Junctionless (JL); Double gate; Process variation; TRANSISTOR;

D O I：

10.1016/j.spmi.2016.06.003

中图分类号：

O469 [凝聚态物理学];

学科分类号：

070205 ;

摘要：

In this work, we propose a junctionless MOSFET with asymmetric gates (AG-JI, MOSFET). This device is a double gate structure with a lateral offset between the gate, and this leads to different characteristic than a conventional double gate structure. Specifically, the asymmetric gate modulates the effective channel length depending on whether the device is in the ON or OFF state, which this leads to more ideal device characteristics. A comprehensive device performance comparison including the l(ON)/I-OFF ratio, subthreshold slope (SS), and drain-induced barrier lowering (DIBL) between the proposed device and a conventional device is presented. The proposed device exhibits superior performance when compared a conventional device, and results show that it is also less sensitive to process variations. (C) 2016 Elsevier Ltd. All rights reserved.

引用

页码：8 / 14

页数：7

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