TSVs in Early Layout Design Exploration for 3D ICs

被引：0

作者：

Ahmed, Mohammad A. ^{[1
]}

Chrzanowska-Jeske, M. ^{[1
]}

机构：

[1] Portland State Univ, Dept Elect & Comp Engn, Portland, OR 97207 USA

来源：

2014 IEEE 5TH LATIN AMERICAN SYMPOSIUM ON CIRCUITS AND SYSTEMS (LASCAS) | 2014年

关键词：

3D Floorplanning; Through-silicon-via; Keep-out-zone; Thermo-mechanical Stress;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

3D-IC technology discussed in this paper is based on vertical stacking of dies connected by through-silicon-vias (TSV). Vertical stacking helps reducing the wirelength but TSVs occupy space on device layers and their actual positions, arrangement, and physical properties determine the total wirelength. They also introduce thermo-mechanical stress that alters properties of devices that are close to them. Keep-Out-Zone (KOZ) around a single TSV or an island of TSVs is needed to eliminate influence of the thermo-mechanical stress. We use 3D floorplanning tool for early layout design exploration. The KOZ for different shapes and sizes of TSV islands is analyzed and included during floorplanning and TSV impact on wirelength is observed. TSV islands are co-place with circuit blocks to optimize footprint, wirelength and number of TSVs for 3D designs.

引用

页数：4

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