FPGA realization of an efficient image scalar with modified area generation technique

Image scaling is extensively utilized in numerous image processing implementations, like digital camera, tablet, mobile phone, and display devices. Image scaling is a technique of enlarge or diminish the image by provided scale factor. Image scaling can also be discussed as image interpolation, image re-sampling, image resizing, and image zooming. This paper introduces VLSI (Very Large Scale Integration) architecture of an accurate and area effectual image scalar. This architecture is applied in HDL language, synthesize and simulation by Xilinx ISE simulation tool. Lastly observe quality and performance measure, in quality measure associate the PSNR value of scaled image to source image. In presentation measure numerous VLSI parameters like type of device, area, computation time, and power. From the solution in quality measure to upsurge the PSNR value by 15% and 9% Image enlargement and reduction correspondingly and diminish 18% combinational logic blocks (CLBs).