Device Requirements and Technology-Driven Architecture Optimization for Analog Neurocomputing

被引：5

作者：

Calayir, Vehbi ^{[1
]}

Pileggi, Larry ^{[1
]}

机构：

[1] Carnegie Mellon Univ, Dept Elect & Comp Engn, Pittsburgh, PA 15213 USA

来源：

IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS | 2015年 / 5卷 / 02期

基金：

美国国家科学基金会;

关键词：

Associative memory; mCell; neurocomputing; ovenized aluminum nitride resonator; NEURAL-NETWORK; MEMORY; CHIP;

D O I：

10.1109/JETCAS.2015.2426497

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Neurocomputers offer a massively parallel computing paradigm by mimicking the human brain. Their efficient use in statistical information processing has been proposed to overcome critical bottlenecks with traditional computing schemes for applications such as image and speech processing, and associative memory. However, large power consumption and high circuit complexity of CMOS-based implementations have precluded adoption of such systems, and have led researchers to explore the use of emerging technologies. Although they provide intriguing properties, previously proposed neurocomputing components based on emerging technologies have not offered a complete and practical solution to efficiently construct an entire system. In this paper we explore the generalized problem of co-optimization of technology and architecture for such systems, and develop a recipe for device requirements and target capabilities. We describe two plausible case study examples, each of which could potentially enable the implementation of an efficient and fully functional analog neurocomputing system.

引用

页码：162 / 172

页数：11

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