A (21150,19050) GC-LDPC Decoder for NAND Flash Applications

被引：27

作者：

Liao, Yen-Chin ^{[1
]}

Lin, Chien ^{[1
]}

Chang, Hsie-Chia ^{[1
]}

Lin, Shu ^{[2
]}

机构：

[1] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu 30010, Taiwan

[2] Univ Calif Davis, Dept Elect & Comp Engn, Davis, CA 95616 USA

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | 2019年 / 66卷 / 03期

关键词：

Globally-coupled LDPC codes; two-phase local/global iterative decoding; emerging memory ECC; PARITY-CHECK CODES; DENSITY; PERFORMANCE; DESIGN;

D O I：

10.1109/TCSI.2018.2875311

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, a (21150, 19050) globally-coupled low-density parity check (GC-LDPC) code designed for NAND flash memories is presented. The proposed LDPC code comprises three disjoint subcodes which can be decoded independently. This highly structural parity check matrix contributes to efficient decoder implementation and flexible decoding flow control. Moreover, a two-phase local/global decoding procedure optimized for the proposed GC-LDPC code is introduced. Scenarios of collaborative decoding that leverages the special code structures are discussed. In the proposed decoder architecture, the pipelined processing elements with scheduling are employed to reduce the critical path and decoding latency as well. Implemented in UMC 65 nm process, the post-layout simulation shows a maximum decoding throughput of 432 Gb/s with the chip area 3.376 mm(2).

引用

页码：1219 / 1230

页数：12

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