A low-power 10-bit CCP-based pipelined ADC using a multi-level variable current source MDAC and an ultra-low-power double-tail dynamic latch

In this paper, a low-power 10-bit 15-MS/s opamp-less pipelined analog-to-digital converter (ADC) has been proposed. The circuit is comprised of eight 1.5-bit/stage MDACs and a 2-bit backend flash ADC. Each 1.5-bit/stage structure comprises a CCP-based MDAC which uses a modified multilevel variable-current-source (ML-VCS) scheme. The modified ML-VCS CCP structure facilitates its usage in a pipeline ADC structure. Also, the proposed ML-VCS structure improves the speed behavior as well as the power consumption of a 1.5-bit/stage CCP-based MDAC structure. In order to further reduce power consumption, an ultra-low-power low-delay double-tail dynamic latch has been offered which features high-speed operation. The suggested ADC is simulated using 180-nm scaled CMOS technology with a 2-Vp-p differential full-scale input voltage. Hspice simulation results show that the ADC exhibits an SNDR of 60-dB, an ENOB of 9.67 bits, and the FOM of 0.546 PJ/Conv.step at a Nyquist-rate input frequency. According to the results, the proposed 10-bit ADC consumes only 6.7-mW under a 1.8-V supply voltage.