A 50 GHz divide-by-4 injection lock frequency divider using matching method

A fully integrated divide-by-4 frequency divider has been designed, fabricated, and measured in the standard bulk 0.18-mu m complementary metal-oxide semiconductor (CMOS) technology. A newly proposed matching technique was used to eliminate the unwanted low frequency mixing terms at the common node of the circuit so as to achieve a high division ratio of 4. The frequency divider exhibits a measured operation range of 5 GHz from 45.9 to 50.9 GHz. It consumes a dc power of 7.56 mW at a 1.2 V supply in the steady state operation. The phase noise of the free running divider is -88.51 dBc/Hz at 1 MHz offset and the locked divider is -110.74 dBc/Hz at I MHz offset. The chip size is only 0.35 min x 0.5 mm including the pad frame. To our knowledge, this divider has the highest operation frequency to date among the high division ratio injection-lock type frequency dividers in commercial CMOS 0.18-mu m process.