SPARK: A high-level synthesis framework for applying parallelizing compiler transformations

被引:139
作者
Gupta, S [1 ]
Dutt, N [1 ]
Gupta, R [1 ]
Nicolau, A [1 ]
机构
[1] Univ Calif Irvine, Ctr Embedded Comp Sys, Irvine, CA 92697 USA
来源
16TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS | 2003年
关键词
D O I
10.1109/ICVD.2003.1183177
中图分类号
TP31 [计算机软件];
学科分类号
081202 ; 0835 ;
摘要
This paper presents a modular and extensible high-level synthesis research system, called SPARK that takes a behavioral description in ANSI-C as input and produces synthesizable register-transfer level VHDL. SPARK uses parallelizing compiler technology developed previously to enhance instruction-level parallelism and re-instruments it for high-level synthesis by incorporating ideas of mutual exclusivity of operations, resource sharing and hardware cost models. In this paper we present the design flow through the SPARK system, a set of transformations that include speculative code motions and dynamic transformations and show how these transformations and other optimizing synthesis and compiler techniques are employed by a scheduling heuristic. Experiments are performed on two moderately complex industrial applications, namely, MPEG-1 and the GIMP image processing tool. The results show that the various code transformations lead to up to 70 % improvements in performance without any increase in the overall area and critical path of the final synthesized design.
引用
收藏
页码:461 / 466
页数:6
相关论文
共 19 条
[1]  
ADIVOJEVIC I, 1996, IEEE T CAD JAN
[2]  
Aho Alfred V., 1986, ADDISON WESLEY SERIE
[3]  
[Anonymous], GNU IMAGE MANIPULATI
[4]  
De Micheli Giovanni, 1994, Synthesis and Optimization of Digital Circuits
[5]  
DOSSANTOS L, 1999, DAC
[6]  
FISHER J, 1981, T COMPUTERS JUL
[7]  
GIRKAR M, 1992, IEEE T PDS MAR
[8]  
GUPTA S, 2001, ISSS
[9]  
GUPTA S, 2001, DAC
[10]  
GUPTA S, 2002, ISSS