Instruction set extension for long integer modulo arithmetic on RISC-based smart cards

被引:12
作者
Grossschädl, J [1 ]
机构
[1] Graz Univ Technol, Inst Appl Informat Proc & Commun, A-8010 Graz, Austria
来源
14TH SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING, PROCEEDINGS | 2002年
关键词
application -specific instruction set processor (ASIP); core-based design; Montgomery multiplication;
D O I
10.1109/CAHPC.2002.1180754
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Modulo multiplication of long integers (greater than or equal to 1024 bits) is the major operation of many public-key crptosystems like RSA or Diffie-Hellman. The efficient implementation of modulo arithmetic is a challenging task, in particular on smart cards due to their constrained resources and relatively slow clock frequency. In this paper we present the concept of air application-specific instruction set extension (ISE) for long integer arithmetic. We introduce an optimized multiply-andaccumulate (MAC) unit that makes it possible to compute a x b+c+d with only one instruction, whereby a, b, c,d are single-precision words (unsigned integers). This additional instruction is simple to incorporate into common RISC architectures like the MIPS32. Experimental results show that the inner-product operation of a multiple-precision multiplication can be accelerated by a factor of two without increasing the processor's clock frequency. We also estimate the execution time of a 1024-bit modulo exponentiation assuming that this special MAC instruction was made available. The proposed ISE is an alternative solution to a crypto co-processor especially for multi-application smart cards (e.g., Java cards) with an embedded 32-bit RISC core.
引用
收藏
页码:13 / 19
页数:7
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