A 1-V 15-Bit Audio ΔΣ-ADC in 0.18 μm CMOS

In this paper a 1-V supply, 15-bit Delta Sigma ADC design for audio applications is presented. The second order CIFB Delta Sigma modulator with a 3-bit internal quantizer is adopted. The design of noise transfer function ( NTF) is discussed from the viewpoint of mitigating the quantization noise mixture effect. A single-capacitor summing circuit is proposed which eliminates additional amplification or deliberate reference scaling. Nonideal effect due to parasitic capacitance is discussed. With proper modulator architecture, the design of building blocks is relaxed. Low gain amplifier with high power efficiency can be adopted which saves power. The decimator is implemented with cascade subfilters. Time multiplexing of arithmetic resources is employed for low hardware cost. Fabricated in 0.18 mu m CMOS, the prototype ADC achieves 91.3 dB peak SNDR with 16 kHz. The modulator dissipates 190 mu W and the decimator consumes 170 mu W. The core area of the ADC is 0.5 mm(2). The modulator occupies 0.3 mm(2) and the decimator occupies 0.2 mm(2).