BIST tool digs into embedded memories

被引：0
|
作者：
Lipman, J
机构：
来源：
EDN | 1997年 / 42卷 / 22期
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：16 / 16
页数：1
相关论文
共 50 条
  • [1] BIST FOR EMBEDDED MEMORIES
    ZORIAN, Y
    EE-EVALUATION ENGINEERING, 1995, 34 (09): : 122 - 123
  • [2] BRAINS: A BIST compiler for embedded memories
    Cheng, C
    Huang, CT
    Huang, JR
    Wu, CW
    IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2000, : 299 - 307
  • [3] Mentor targets embedded memories with BIST.
    不详
    COMPUTER DESIGN, 1996, 35 (07): : 126 - 126
  • [4] Optimizing BIST and Repair Logic for Embedded Memories
    Karunaratne, Maddumage
    Oomann, Bejoy
    2008 51ST MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2, 2008, : 350 - +
  • [5] Testing embedded memories: Is BIST the ultimate solution?
    Wu, CW
    SEVENTH ASIAN TEST SYMPOSIUM (ATS'98), PROCEEDINGS, 1998, : 516 - 517
  • [6] A BIST-based charge analysis for embedded memories
    Alorda, B
    Canals, V
    de Paúl, I
    Segura, J
    10TH IEEE INTERNATIONAL ON-LINE TESTING SYMPOSIUM, PROCEEDINGS, 2004, : 199 - 204
  • [7] Charge-based testing BIST for embedded memories
    Alorda, B.
    de Paul, I.
    Segura, J.
    IET COMPUTERS AND DIGITAL TECHNIQUES, 2007, 1 (05): : 481 - 490
  • [8] Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories
    Denq, Li-Ming
    Hsing, Yu-Tsao
    Wu, Cheng-Wen
    IEEE DESIGN & TEST OF COMPUTERS, 2009, 26 (02): : 64 - 72
  • [9] A scan-bist environment for testing embedded memories
    Karimi, F
    Lombardi, F
    PROCEEDING OF THE 2002 IEEE INTERNATIONAL WORKSHOP ON MEMORY TECHNOLOGY, DESIGN AND TESTING, 2002, : 17 - 23
  • [10] A hybrid BIST scheme for multiple heterogeneous embedded memories
    Denq, Li-Ming
    Wu, Cheng-Wen
    PROCEEDINGS OF THE 16TH ASIAN TEST SYMPOSIUM, 2007, : 349 - 354
12345