Memristor ratioed logic crossbar-based delay and jump-key flip-flops design

Memristor has been widely explored in digital logic circuits where most of the works are focused on basic gate circuits, such as OR and AND logic gates or full adders while few involve flip-flops. In fact, flip-flops are also basic logic units with memory function for various digital systems. In this paper, we present circuit designs for Delay (D) and Jump-Key (JK) flip-flops based on memristor ratioed logic (MRL). The proposed circuit for D flip-flop only needs five memristors and one NMOS transistor, and circuit for JK flip-flop needs seven memristors and two NMOS transistors. Furthermore, the proposed circuits have been mapped into a hybrid memristor-CMOS crossbar array. Compared with previous approaches, the quantity of MOSFET for each proposed circuit has been greatly reduced. Thus, the proposed designs have achieved simpler structure, smaller area, and lower power consumption benefiting from the memristor's nanoscale size and low power consumption. The circuit verification based on PSpice simulation is also provided.